RF Interface

TX_ENV

RF_PWR

PLLSW

ANT_SW

TX_DATA

4.0us

4.0us

4.0us extension

of last chip*

Transition at Received End only - synchronous with PLLSW

420us - typical

RF

Interface

* Control signal window is inversely proportional to input clock. 4.0us is calibrated at 19.2MHz.

** Connect BSYNC_IN to BSYNC_OUT for single master operation. See details in the data sheet for multi-master timing.

BSYNC_IN**

BSYNC_OUT**

Previous slide

Next slide

Back to first slide

View graphic version