CSR2
T/N: Test / Normal bit. Set to 0 during normal operation.
M/S: Master / Slave control bit. Set to 1 for Master TDD operation, 0 otherwise.
RE: Enable Receive End Interrupt. When set to 1 along with SUBE, enables all subframe
as well as Receive End Interrupts.
TE: Enable Transmit End Interrupt. When set to 1 along with SUBE, enables all subframe
as well as Transmit End Interrupts.
CSR2[7:5] These 3 bits must be programmed to zero.